The manufacture of integrated circuits (IC) is becoming ever more complicated as finer and finer geometries are designed into today's semiconductor ICs. For example, as manufacturing processes become more complex due to the finer geometries, the physical and electrical variance between ICs fabricated on the same wafer become more difficult to control. The variance can even increase as different ICs are manufactured on a single wafer. These variances can contribute greatly to performance differences between otherwise identical IC chips, which, in turn, can affect downstream assemblies, e.g., (next level manufacturing). For these and other reasons, IC designs must account for processing differences such as, for example, variations in temperature and voltage within specified windows at system level to insure function of the final product.
As a result of such variations, the performance specification window for ICs is currently very wide. Such windows include ICs built with best case process bias (BCPB) and worst case process bias (WCPB). But, using ICs with BCPB and WCPB on a same card or system can degrade performance of the assembly. For example, transistor devices built with BCPB leak more DC current under static conditions contributing significantly to IC power consumption at a fixed voltage, while providing performance above that needed at system level. Transistor devices built with WCPB, on the other hand, consume very little power at the same fixed voltage, while being challenged to meet the performance requirements of the system. Thus, as a card or system manufacturer assembles a single system with ICs built from both BCPB and WCPB, some subset of ICs will operate at or near their functional limit while others are burning more power than is required to operate at the system frequency.
As such, while the IC designer must negotiate the IC fabrication processes, the card or system designer must successfully integrate a number of ICs into a functional next level assembly. However, the ICs which are to be integrated more than likely are manufactured by different IC manufacturers at different times with different processes. This being the case, the card or system designed must function with any mix of ICs provided by the IC suppliers, as a mix of ICs with BCPB, WCPB or nominal process bias (NPB) may exist in the assembly.
In a known method, IC suppliers may performance sort or screen ICs during IC final test to insure that ICs which do not meet a specified performance at a given temperature and voltage are not shipped to the assembler, or that ICs be grossly binned into fast and slow subsets to be used for different system performance levels. But these methods subtract from IC yield, add to inventory costs and prove difficult for next level manufacturing as the number of ICs in the card or system grows due to the functional complexity of such cards or systems. As to the latter issue, for example, IC manufacturers may not be able to provide enough “fast” or “low power” product to keep the next level of manufacturing on schedule. Additionally, such methods do not guarantee that power is minimized at the required performance level for the IC.
Also, to guarantee functionality, the card/system designer must achieve timing closure accounting for maximum performance skew between the various ICs in the assembly. This requirement generally results in a degradation of performance specifications relative to the ideal that would be possible if all ICs could be guaranteed to be at the same performance level during system/card level integration.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.